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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com advanced product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. 114 db, 192 khz, 8-ch annel a/d converter overall features ! advanced multi-bit delta-sigma architecture ! 24-bit conversion ! 114 db dynamic range ! -105 db thd+n ! supports audio sample rates up to 216 khz ! selectable audio interface formats ? left-justified, i2s, tdm ? 8-channel tdm interface formats ! low latency digital filter ! less than 600 mw power consumption ! on-chip oscillator driver ! operation as system clock master or slave ! differential analog architecture ! separate 1.8 v to 5 v logic supplie s for control and serial ports ! high-pass filter for dc offset calibration ! overflow detection ! pin-compatible with the 4-channel cs5364 and 6-channel cs5366 additional control port features ! supports standard i2c or spi control interface ! individual channel hpf disable ! overflow detection for individual channels ! mute control for individual channels ! independent power-down control per channel pair di gital audio internal oscillator level translator level translator voltage reference vd 3.3 - 5v control interface i 2 c, spi or pins configuration regi sters vlc 1.8 - 5v vls 1.8 - 5v 8 differential analog inputs device control deci mati on filter hi gh pass filter serial audio out pcm or tdm va 5v multi-bit ? adc july '05 ds624a1 cs5368
2 ds624a1 cs5368 description the cs5368 is a complete 8-channel analog-to-digital conver ter for digital audio systems. it performs sampling, an- alog-to-digital conversion and anti-alias filtering, generati ng 24-bit values for all 8-channel inputs in serial form at sample rates up to 216 khz per channel. the cs5368 uses a 5th-order, multi-bit delta sigma modula tor followed by low latency di gital filtering and decima- tion, which removes the need for an external anti-aliasing f ilter. the adc uses a differenti al input architecture which provides excellent noise rejection. dedicated level translators for the serial port and contro l port allow seamless interf acing between the cs5368 and other devices operating over a wide rang e of logic levels. in addition, an on-c hip oscillator driver provides clocking flexibility and simplifies design. the cs5368 is the industry?s first audio a/d to support a high-speed tdm interface which provides a serial output of 8 channels of audio data with sample rates up to 216 khz within a single data stream . it further reduces layout complexity and relieves input/output cons traints in digital signal processors. the cs5368 is ideal for high-end and pro-audio systems r equiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as a/v receivers, digital mixing consoles, multi-channel record- ers, outboard converters, digital effect processors, and automotive audio systems. ordering information product description package pb-free grade temp range container order # cs5368 114db, 192khz, 8-channel a/d con- verter 48-pin lqfp yes commercial -10 to +85c tray CS5368-CQZ tape & reel CS5368-CQZr automotive -40 to +85c tray cs5368-dqz tape & reel cs5368-dqzr cdb5368 evaluation board for cs5368 cdb5368
ds624a1 3 cs5368 table of contents 1. pin description ...................................................................................................... 9 2. characteristics and speci fications........... ................................ ............... 13 specified operating conditions .............................................................................................. 13 absolute ratings ............................................................................................................... ..... 13 system clocking ................................................................................................................ ..... 13 thermal characteristics.................................... .................................................................... .. 13 dc power cs5368 ................................................................................................................ .14 logic levels .................................................................................................................. ......... 14 psrr, vq and filt+ characteristics ..................................................................................... 14 analog performance (CS5368-CQZ)...................................................................................... 15 analog performance (cs5368-dqz)...................................................................................... 16 digital filter characteristics ................................................................................................ ... 17 serial audio interface - i2s/lj timing ..................................................................................... 18 serial audio interface - tdm timing....................................................................................... 19 overflow timeout ............................................................................................................... .... 19 switching specifications - control port - i2c timing ............................................................... 20 switching specifications - control port - spi timing .............................................................. 21 3. typical connection diagram ....................................................................... 23 3.1 suggested analog input buffer................... ...................................................................... 24 4. applications ......................................................................................................... 25 4.1 power ...................................................................................................................... ......... 25 4.2 clocking ................................................................................................................... ......... 25 4.3 stand-alone operation ..................................................................................................... 2 6 4.4 control-port operation ..................................................................................................... 26 4.5 dc offset control .......................................................................................................... ... 26 4.6 serial audio interface (sai) .............................................................................................. 2 6 4.6.1 general description ............................. ................................................................ 26 4.6.2 master and slave operation ................................................................................ 26 4.6.3 synchronization of multiple devices .................................................................... 27 4.6.4 sample rate ranges........................................................................................... 27 4.6.5 using m1 and m0 to set sampling parameters................................................... 27 4.6.6 using dif1 and dif0 to set serial audio interface format ................................. 28 4.6.7 master mode audio clocking ............................................................................... 28 4.6.8 slave mode audio clocking ................................................................................. 28 4.6.9 master and slave clock frequencies .................................................................. 29 4.7 serial audio formats ....................................................................................................... .30 4.7.1 lj and i2s format ............................................................................................ 31 4.7.2 tdm format......................................................................................................... 31 4.8 overflow detection ..................................... .................................................................... .. 31 4.8.1 stand-alone mode ............................................................................................... 31 4.8.2 control-port mode................................................................................................ 31 4.9 control port operation..................................................................................................... .31 4.9.1 spi mode ............................................................................................................. 31 4.9.2 i2c mode .............................................................................................................. 32 5. register map......................................................................................................... 35 5.1 register quick reference ............................................................................................... 35 5.2 00h (revi) chip id code & revision register................................................................. 35 5.3 01h (gctl) global mode control register ..................................................................... 35
4 ds624a1 cs5368 5.4 02h (ovfl) overflow status register ............................................................................. 36 5.5 03h (ovfm) overflow mask register .............................................................................. 37 5.6 04h (hpf) high-pass filter register ......... ...................................................................... 37 5.7 05h reserved .............................................................................................................. .... 37 5.8 06h (pdn) power down register .............. ...................................................................... 37 5.9 07h reserved .............................................................................................................. .... 38 5.10 08h (mute) mute control register .......... ...................................................................... 38 5.11 09h reserved ............................................................................................................. ... 38 5.12 0ah (sden) sdout enable control register .............................................................. 38 appendix a digital filter plots .................................................................................... 39 appendix b parameter definitions .............................................................................. 43 appendix c package dimensions .............................................................................. 45
ds624a1 5 cs5368 list of figures figure 1. cs5368 pinout........................................................................................................ ......... 9 figure 2. i2s/lj timing........................................................................................................ .......... 18 figure 3. tdm timing ........................................................................................................... ........ 19 figure 4. i2c timing ........................................................................................................... ........... 20 figure 5. spi timing ........................................................................................................... .......... 21 figure 6. typical connection diagram.......................................................................................... 2 3 figure 7. recommended analog input buffer............................................................................... 24 figure 8. crystal oscillator topo logy .......................................................................................... .. 25 figure 9. master slave clock flow .............................................................................................. .27 figure 10. master and slave cloc king for a 32-channel application............................................ 27 figure 11. master mode clock dividers ........................................................................................ 28 figure 12. lj format........................................................................................................... .......... 30 figure 13. i2s format .......................................................................................................... .......... 30 figure 14. tdm format.......................................................................................................... ....... 30 figure 15. spi format.......................................................................................................... ......... 32 figure 16. i2c write format ................................................................................................... ...... 33 figure 17. i2c read format ..................................................................................................... ..... 33 figure 18. ssm passband ........................................................................................................ .... 39 figure 19. dsm passband ........................................................................................................ .... 39 figure 20. qsm passband........................................................................................................ .... 39 figure 21. ssm stopband........................................................................................................ ..... 40 figure 22. dsm stopband........................................................................................................ ..... 40 figure 23. qsm stopband ........................................................................................................ .... 40 figure 24. ssm -1 db cutoff .................................................................................................... ..... 41 figure 25. dsm -1 db cutoff.................................................................................................... ..... 41 figure 26. qsm -1 db cutoff.................................................................................................... ..... 41
ds624a1 7 cs5368 list of tables table 1. overflow timeout ...................................................................................................... ...... 19 table 2. m1 and m0 settings .................................................................................................... .... 27 table 3. dif1 and dif0 pin settings ............................................................................................ 28 table 4. frequencies for 48 khz sample rate us ing lj/i2s ......................................................... 29 table 5. frequencies for 96 khz sample rate us ing lj/i2s ......................................................... 29 table 6. frequencies for 192 khz sample rate us ing lj/i2s ....................................................... 29 table 7. frequencies for 48 khz sample rate us ing tdm........................................................... 29 table 8. frequencies for 96 khz sample rate us ing tdm........................................................... 30 table 9. frequencies for 192 khz sample rate us ing tdm......................................................... 30 table 10. revision history .................................................................................................... ....... 47
ds624a1 9 cs5368 1. pin description figure 1. cs5368 pinout ain3+ sdout1/tdm vls sdout4/tdmc sdout3/tdm gnd sdout2/tdmc m0/sda/cdout ain5- ain1+ ain5+ ain6- ain6+ ain3- ain7+ ain7- ain8- xti xto mclk ain8+ vlc dif0/ad0/cs dif1/ad1/cdin ain1- m1/scl/cclk vx sclk lrck/fs ovfl gnd mdiv rst 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 cs5368 filt+ ain2- va gnd gnd ain2+ gnd ref_gnd va ain4+ ain4- vq gnd vd clkmode
10 ds624a1 cs5368 pin name pin # pin description ain2+ain2- ain4+ain4- ain3+ain3- ain7+ain7- ain8+ain8- ain6+ain6- ain5+ain5- ain1+ain1- 1,2, 11,12 13,14 15,16 17,18 43,44 45,46 47,48 differential analog ( inputs ) - audio signals are presented differently to the delta sigma modulators via the ain+/- pins. gnd 3,8 10,19 29,32 ground ( input ) ground reference. must be connected to analog ground. va 4,9 analog power ( input ) - positive power supply for the analog section vq 7 quiescent voltage ( output ) - filter connection for the internal quiescent reference voltage. vx 20 xtal power vls 28 serial audio interface power - positive power for the serial audio interface. vd 33 digital power ( input )- positive power supply for the digital section/ vlc 35 control port interface power - positive power for the control port interface. ref_gnd 5 reference ground ( input ) - for the internal sampling circuits. filt+ 6 positive voltage reference ( output ) - reference voltage fo r internal sampling cir- cuits. xtixto 21 22 crystal oscillator connections ( input/output ) - i/o pins for an external crystal which may be used to generate mclk. mclk 23 system master clock ( input/output ) - when a crystal is used, this pin acts as a buff- ered mclk source (output). when the oscillato r function is not used, this pin acts as an input for the system master clock. in this case, the xti and xto pins must be tied low. lrck/fs 24 serial audio channel clock ( input/output ) in i2s mode serial audio channel select. when high, the odd channels are selected. in lj mode serial audio channel select. when low, the odd channels are selected. in tdm mode a frame sync signal. when high, it marks the beginning of a new frame of serial audio samples. in slave mode , this pin acts as an input pin. sclk 25 main timing clock for the serial audio interface ( input/output ). during master mode, this pin acts as an output, and during slave mode it acts as an input pin. sdout4/tdmc 26 serial audio data ( output ) channels 7,8. sdout2/tdmc 27 serial audio data ( output ) channels 3,4. sdout1/tdm 30 serial audio data ( output ) channels 1,2. sdout3/tdm 31 serial audio data ( output ) channels 5,6. ovfl 36 overflow ( output, open drain ) - detects an overflow condition on both left and right channels. rst 41 reset ( input ) - the device enters a low power mode when low.
ds624a1 11 cs5368 stand-alone mode clkmode 34 clkmode (input) setting this pin high places a divide-by-1.5 circuit in the mclk path to the core device circuitry. dif1, dif0 37, 38 dif1, dif0 ( input ) - inputs of the audio interface format. m1, m0 39,40 mode selection ( input ) - determines the operational mode of the device. mdiv 42 mclk divider ( input ) setting this pin high places a divide-by-2 circuit in the mclk path to the core device circuitry. control port mode clkmode 34 clkmode (input) this pin is ignored in control po rt mode and the same functionality is obtained from the corresponding bit in the global control register. note: should be connected to gnd. ad1/cdin 37 i2c format, ad1 ( input ) - forms the device address input ad[1]. spi format, cdin ( input ) - becomes the input data pin. ad0/cs 38 i2c format, ado ( input ) - forms the device address input ad[0]. spi format, cs (input) - acts as the acti ve low chip select input. scl/cclk 39 i2c format, scl ( output ) - acts as the serial clock output from the cs5368. spi format, cclk ( output ) - acts as the serial clock output from the cs5368. sda/cdout 40 i2c format sda ( input/output ) - acts as an input/output data pin. spi format cdout ( output ) - acts as an output only data pin . mdiv 42 mclk divider ( input ) this pin is ignored in control port mode and the same function- ality is obtained from the corresponding bit in the global control register. note: should be connected to gnd.
ds624a1 13 cs5368 2. characteristics and specifications all min/max characteristics and specifications are guaran teed over the specified operat ing conditions. typical per- formance characteristics and specificat ions are derived from measurements ta ken at typical supply voltages and t a = 25 c. specified operating conditions gnd = 0 v, all voltages with respect to 0 v. 1. tdm quad-speed mode specified to operate correctly at vls 3.14 v. absolute ratings operation beyond these limits may result in permanent da mage to the device. normal operation is not guaranteed at these extremes. transient currents up to 100 ma on the analog input pins w ill not cause scr latch-up. system clocking thermal characteristics parameter symbol min typ max unit dc power supplies: positive analog positive crystal positive digital positive serial logic positive control logic va vx vd vls vlc 4.75 4.75 3.14 1.71 1 1.71 5.0 5.0 3.3 3.3 3.3 5.25 5.25 5.25 5.25 5.25 v v v v v ambient operating temperature (-cqz) (-dqz) t ac t aa -10 -40 - - 85 85 c c parameter symbol min typ max units dc power supplies: positive analog positive crystal positive digital positive serial logic positive control logic va vx vd vls vlc -0.3 -0.3 -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 +6.0 +6.0 v v v v v input current i in - 10 ma analog input voltage v in -0.3 va+0.3 v v digital input voltage v ind -0.3 vl+0.3 ambient operating temperature (power applied) t a -50 +95 c c storage temperature t stg -65 +150 parameter symbol min typ max unit input master clock frequency mclk 0.512 55.05 mhz input master clock duty cycle t clkhl 40 60 % parameter symbol min typ max unit allowable junction temperature - - 135 c package thermal resistance ja -48- c/w c/w jc -15-
14 ds624a1 cs5368 dc power cs5368 mclk = 12.288 mhz; master mode. power down is defined as rst = low with all clocks and data lines held static. gnd = 0 v. logic levels psrr, vq and filt + characteristics mclk = 12.288 mhz; master mode. valid with the recomme nded capacitor values on filt+ and vq as shown in the ?typical connection diagram?. parameter symbol min typ max unit power supply current va = 5 v (normal operation) vx = 5 v vd = 5 v vd = 3.3 v vls, vlc = 5 v vls, vlc = 3.3 v i a i x i d i d i l i l - - - - - - 70 4 88 58 8 5 77 8 97 64 9 6 ma ma ma ma ma ma power supply current va = 5 v (power-down) vls, vlc,vd = 5 v i a i d - - 2 2 - - ma ma power consumption (normal operation) all supplies = 5 v va = 5 v, vd = vls = vlc = 3.3 v (power-down) - - - - - - 830 558 35 915 616 - mw mw mw mw parameter symbol min typ max units high-level input voltage %vls/vlc v ih 70 - - % % low-level input voltage %vls/vlc v il -30 high-level output voltage at 100 a load %vls/vlc v oh 85 - - % % low-level output voltage at -100 a load %vls/vlc v ol --15 ovfl current sink -4 ma input leakage current logic pins only i in -- 10 a parameter symbol min typ max unit power supply rejection ratio at 1 khz) psrr - 65 - db v q nominal voltage output impedance maximum allowable dc current source/sink - - - va/2 25 10 - - - v k ? a filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 4.4 10 - - - v k ? a
ds624a1 15 cs5368 analog performance (CS5368-CQZ) unless otherwise specified, input test signal is a 1 k hz sine wave. measurement bandwidth is 10 hz to 20 khz. parameter symbol min typ max unit single-speed mode (fs = 48 khz) dynamic range a-weighted unweighted 108 105 114 111 - - db db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db thd+n - - - -105 -91 -51 -99 - - db db db double-speed mode (fs = 96 khz) dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 - - - db db db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1db thd+n - - - - -105 -91 -51 -102 -99 - - - db db db db quad-speed mode (fs = 192 khz) dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 - - - db db db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1db thd+n - - - - -105 -91 -51 -102 -99 - - - db db db db dynamic performance for all modes interchannel isolation - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error - - 5% gain drift - 100 - ppm/c offset error hpf enabled hpf disabled 0 - - - - 100 lsb lsb analog input characteristics full-scale different ial input voltage (at va = 5v) 1.07*va 1.13*va 1.19*va vpp input impedance (differential) -7.5-k ? common mode reject ion ratio cmrr - 82 - db
16 ds624a1 cs5368 analog performance (cs5368-dqz) unless otherwise specified, in put test signal is a 1 khz sine wave. measurement bandwidth is 10 hz to 20 khz. parameter symbol min typ max unit single-speed mode fs = 48 khz dynamic range a-weighted unweighted 106 103 114 111 - - db db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db thd+n - - - -105 -91 -51 -97 - - db db db double-speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 106 103 - 114 111 108 - - - db db db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -105 -91 -51 -102 -97 - - - db db db db quad-speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 106 103 - 114 111 108 - - - db db db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -105 -91 -51 -102 -97 - - - db db db db dynamic performance for all modes interchannel isolation - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error - - 7% gain drift - 100 - ppm/c offset error hpf enabled hpf disabled 0 - - - - 100 lsb lsb analog input characteristics full-scale input voltage (at va = 5.0 v) 1.02*va 1.13*va 1.24*va vpp input impedance (differential) 7.5 - k ? common mode rejection ratio cmrr - 82 - db
ds624a1 17 cs5368 digital filter characteristics parameter symbol min typ max unit single-speed mode (2 khz to 54 khz sample rates) passband (-0.1 db) 0 - 0.47 fs passband ripple - - 0.035 db stopband 0.58 - - fs stopband attenuation -95 - - db total group delay (fs = output sample rate) t gd -12/fs-s double-speed mode (54 khz to 108 khz sample rates) passband (-0.1 db) 0 - 0.45 fs passband ripple - - 0.035 db stopband 0.68 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -9/fs-s quad-speed mode (108 khz to 216 khz sample rates) passband (-0.1 db) 0 - 0.24 fs passband ripple - - 0.035 db stopband 0.78 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -5/fs-s high-pass filter characteristics frequency response -3.0 db -0.13 db - - 1 20 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple - - 0 db filter settling time - 10 5 /fs - s
18 ds624a1 cs5368 serial audio interface - i2s/lj timing the serial audio port is a three-pin inte rface consisting of sclk, lrck and sdout. logic "0" = gnd = 0 v; logic "1" = vls; c l = 30 pf, timing threshold is 50% of vls. notes: 1. in master mode, the sclk/lrck ratio is fixed at 64. in slave mode, the sclk/rclk ratio can be set ac- cording to preference. however, chip performanc e is guaranteed only when using the ratios in section 4.6.9 master and slave clock frequencies on page 29 . figure 2. i2s/lj timing parameter symbol min typ max unit sample rates single-speed mode double-speed mode quad-speed mode - - - 2 54 108 - - - 54 108 216 khz khz khz sclk frequency 1 sclk period 1/(64*216 khz) sclk duty cycle - t period t high - 72.3 30 64*fs - - - - 70 hz ns % lrck setup before sclk rising lrck hold after sclk rising t setup1 t hold1 20 20 - - - - ns ns sdout setup before sclk rising sdout hold after sclk rising t setup2 t hold2 10 10 - - - - ns ns lrck sdout sclk data channel channel data t hold2 t setup2 t hold1 t setup1 t period t high
ds624a1 19 cs5368 serial audio interface - tdm timing the serial audio port is a 3 pin interface consisting of sclk, lrck and sdout. logic "0" = gnd = 0 v; logic "1" = vls; c l = 20 pf, timing threshold is 50% of vls. notes: 1. tdm quad-speed mode only specified to operate correctly at vls 3.14 v. 2. in master mode, the sclk/lrck ratio is fixed at 256. in slave mode, the sclk/rclk ratio can be set according to preference. however, chip performanc e is guaranteed only when using the ratios in section 4.6.9 master and slave clock frequencies on page 29 . figure 3. tdm timing overflow timeout logic "0" = gnd = 0 v; logic "1" = vls; c l = 15 pf, timing threshold is 50% of vls. table 1. overflow timeout parameter symbol min typ max unit sample rates single-speed mode double-speed mode quad-speed mode 1 - - - 2 54 108 - - - 54 108 216 khz khz khz sclk frequency 2 sclk period 1/(256*54 khz) sclk duty cycle t period t high1 - 72.3 30 256*fs - - - - 70 hz ns % fs setup before sclk rising fs hold after sclk rising fs width in sclk cycles t setup1 t hold1 t high2 20 20 3 - - - - - 250 ns ns - sdout setup before sclk rising sdout hold after sclk rising t setup2 t hold2 10 10 - - - - ns ns parameter symbol min typ max unit ovfl time-out on overrange condition fs = 44.1 khz fs = 192 khz - - - (2 17 -1)/fs 2972 683 - - - ms ms ms fs sdout sclk data data t hold2 t setup2 t hold1 t setup1 new frame data t period t high1 t high2
20 ds624a1 cs5368 switching specificat ions - control po rt - i2c timing (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5.0 v; inputs: logic 0 = dgnd, logic 1 = vlc, sda c l =30pf) notes: 1. data must be held for sufficient ti me to bridge the transition time, t fc , of scl figure 4. i2c timing parameter symbol min max unit scl clock frequency f scl -100khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling 1 t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t lo w t hdd t high t sud stop sta rt sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack
ds624a1 21 cs5368 switching specifications - control port - spi timing (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5. 0 v; inputs: logic 0 = dgnd, logic 1 = vlc, cdout c l =30pf) notes: 1. data must be held for sufficient time to bridge the transition time of cclk. 2. for f sck <1 mhz 3. for f sck <1 mhz. figure 5. spi timing parameter symbol min max units cclk clock frequency f sck 06.0mhz rst rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 - ns cs high time between transmissions t csh 1.0 - s cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time 1 t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin 2 t r2 - 100 ns fall time of cclk and cdin 3 t f2 -100ns cs cclk cdin cdout rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh t pd
ds624a1 23 cs5368 3. typical connec tion diagram figure 6. typical connection diagram for analog buffer configurations, refer to cirrus application note an241. also, a low cost single ended to differential solution is provided on the customer evaluation board. filt+ d + va v +5v 5.1 ? 1 f + sdout2/ tdmc dif0/ad0/cs power down and mode settings 0.01 f mode0/sda/cdout mode1/scl/cclk ref_gnd vlc f ain + 1 ain - 1 channel 1 analog input buffer ain + 2 ain - 2 channel 2 analog input buffer ain + 3 ain - 3 channel 3 analog input buffer ain + 4 ain - 4 channel 4 analog input buffer ain + 5 ain - 5 channel 5 analog input buffer ain + 6 ain - 6 channel 6 analog input buffer ain + 7 ain - 7 channel 7 analog input buffer ain + 8 ain - 8 channel 8 analog input buffer 0.1 f vq gnd 220 f 0.1 f + 1 f gnd dif1/ad1/cdin rst ovfl 0.01 0.01 f 0.01 f +5v to 3.3v 1 f + a/d converter cs5368 sdout1/ tdm sdout3/ tdm sdout4/ tdmc sclk mclk timing logic and clock audio data processor mdiv clkmode 39 40 36 37 38 41 42 34 30 27 31 26 24 25 23 lrck/fs +5v to 1.8v 6 5 7 8 47 48 1 2 13 14 11 12 45 46 43 44 15 16 17 18 3, 8, 10, 19, 29, 32 33 4, 9, 20 35 vls f 0.01 28 xti xto 21 22 * * resistor may only be used if vd is derived from va. if used, do not drive any other logic from vd. +5v to 1.8v +5v vx 20
24 ds624a1 cs5368 3.1 suggested analog input buffer figure 7. "recommended analog input buffer" shows a recommended analog input buffer for a differential to differential topology. for additional configurations, refer to crystal application note number an241. a low-cost, single-ended (rca jack) to differential solution is shown in the schematics of the customer eval- ution board datasheet (cdb5368). figure 7. recommended analog input buffer vq + 634 ? 634 ? 91 ? 91 ? + - - 2700 pf 470 pf 470 pf cog cog 10 uf 10 uf adc ain+ adc ain- ain+ ain- cog 100 k ? 10 k ? 10 k ? 100 k ?
ds624a1 25 cs5368 4. applications 4.1 power for convenient interfacing to external devices, ther e are five independent power pins for the cs5368. vd powers the digital core. va powers the analog core. vls powers the serial audio interface. vlc powers the control logic. vx powers the cr ystal oscillator. the power pins ma y have any supporte d voltage range of the specified voltages supplied simultaneously. to meet full performance specifications, the cs53 68 requires normal low noise board layout. the ?typical connection diagram? on page 23 shows the recommended power arrangements, with va connected to a clean supply. vd, which powers the digital filter, may be run from the system logic supply, or it may be pow- ered from the analog supply via a single-pole decoupling filter. decoupling capacitors should be placed as near to the adc as possible, with the lower value high frequency capacitors being placed nearest to the device leads. clocks should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the device. the filt+ and vq decoupling capacitors must be positioned to minimize the electrical path to ground. the cdb5368 evaluation board demonstrat es an optimum layout for the device. 4.2 clocking the device supports clocking through the use of either an on-board crystal oscillato r driver or an externally supplied clock. when using the on-board crystal driver, the topology shown in figure 8. "crystal oscillator topology" must be used. the crystal oscillator manufacture r supplies recommended capacitor values. figure 8. crystal oscillator topology when using the on -board crystal oscillator driver, the xti pin is the input fo r the master cloc k (mclk) to the device. the xto pin must not be used to drive anything other than the osc illator tank circuitry. instead, a buffered copy of xti is available on the mclk pin, which is level controlled by vls and may be used to synchronize other parts to the device. if an external clock is used, the xti and xto pins must be grounded, and the mclk pin becomes an input for the system master clock. the cs5368 provides on board master clock dividers that precede all ot her internal clocking. the available dividers are divide by 1, 1.5, 2, 3, 4. xti xto 22 21
26 ds624a1 cs5368 4.3 stand-alone operation in stand-alone mode, the cs5368 is programmed exclus ively with multi-use configuration pins. this mode provides a set of commonly used features. to ut ilize the complete set of device features, cont rol-port mode needs to be used. to use the cs5368 in stand-alone mode, the configurat ion pins must be held in a stable state and rst must be asserted until the power supplies and clocks are stable. upon de-assertion of rst the state of the configuration pins are latched, vq stabilizes and the device st arts sending a udio output data. 4.4 control-port operation in control-port mode, all features of the cs5368 ar e available. four multi-us e configuration pins become software pins that support the i2c or spi bus protocol. to initiate control-port mode, a controller that sup- ports i2c or spi must be used to enable the internal register functionality. this is done by setting the cp-en bit (bit 7 of the global control port register). once cp-en is set, all of the device configuration pins are ignored, and the internal register settings determine the operating modes of the part. 4.5 dc offset control the cs5368 includes a dedicated high-pa ss filter for each channel to remo ve input dc offset at the system level. if a dc level is pres ent, clicks might be heard when switchin g between devices in a multichannel sys- tem. in standalone mode, all of the high pass filters remain enabled. in control-port mode, the high pass filters default to enabled, but may be controlled by writing to the hpf register. if any hpf bit is taken low, the re- spective high-pass filter is enabled, and it continuously subtracts a measure of the dc offset from the output of the decimation filter. if any hpf bit is taken high during device operat ion, the value of the dc offset reg- ister is frozen, and this dc offs et will continue to be subtracted from the conversion result. 4.6 serial audio interface (sai) 4.6.1 general description the sai port consists of two timing pins, sclk , lrck/fs, and four audio data output pins, sdout1/tdm, sdout2/tdm , sdout3/tdmc and sdout4/tdmc . the sai port may be operated as a timing master or a timing slave. the port supplies di gital audio data in three standard formats, lj, i2s and tdm. three sampling ranges are used to provide analog to digital audio conversion from 2 khz to 216 khz sampling rates. the main tdm output port resides on the sdout1 pin. the remaining three tdm outputs are used to balance device substrate noise. it is recommended that all four of these nets be routed and loaded iden- tically for best device noise performance. 4.6.2 master and slave operation in master mode, the cs5368 outputs sclk and lrck /fs which are synchronously derived from mclk. sclk is the audio clock which shifts out the individual bits of each sample. in lj and i2s format, lrck/fs signifies which channel of data is being shifted out. in tdm mode, lrck/fs acts as a frame synchroni- zation signal. a high transition indicates the beginning of a new frame of 8 channels of serial data. in slave mode, sclk and lrck/fs become inputs, and the signals must be supplied by another device. the device may be another cs5368 or a microcontroller. serial data is shifted out by the cs5368 in both cases.
ds624a1 27 cs5368 figure 9. master slave clock flow 4.6.3 synchronization of multiple devices to ensure synchronous sampling in applications w here multiple adcs are used, the mclk and lrck must be the same for all of the cs5368s in the syste m. if only one master clock source is needed, one solution is to place one cs5368 in master mode, an d slave all of the other dev ices to the one master. if multiple master clock sources are needed, a possible so lution would be to supply all clocks from the same external source and time the cs 5368 reset de-assertion wi th the falling edge of mclk. this will ensure that all converters begin sampling on the same clock edge. figure 10. master and slave clo cking for a 32-channel application 4.6.4 sample rate ranges supported sampling rates are 2 khz -216 khz divided into three ranges: 2 khz-54 khz, 54 khz-108 khz, and 108 khz-216 khz. these sampling speed modes are called single-speed mode, double-speed mode and quad-speed mode (ssm, dsm, qsm), respectively. 4.6.5 using m1 and m0 to set sampling parameters the master/slave operation and the sample rate ran ge are controlled through the settings of the m1 and m0 pins in stand-alone mode, or by the m[1] and m[0] bits in the global mode control register in control- port mode. table 2. m1 and m0 settings m1 m0 mode frequency range 0 0 single-speed master mode 2 khz - 54 khz 0 1 double-speed master mode 54 khz - 108 khz 1 0 quadruple-speed master mode 108 khz - 216 khz 1 1 auto-detected speed slave mode 2 khz - 216 khz adc as timing master controller lrck sclk adc as timing slave controller lrck sclk master cs5368 slave1 cs5368 slave2 cs5368 slave3 cs5368 sclk & lrck/fs
28 ds624a1 cs5368 4.6.6 using dif1 and dif0 to se t serial audio interface format the format of the data at the serial audio interface por ts is controlled by the settings of the dif1 and dif0 pins in standalone mode, or by the dif[1] and dif[0] bits in the global mode control register in control- port mode. . table 3. dif1 and dif0 pin settings 4.6.7 master mode audio clocking figure 11. "master mode clock dividers" shows the configuration of th e mclk dividers and the sample rate dividers while in master mode. figure 11. master mode clock dividers 4.6.8 slave mode audio clocking in slave mode, the sampling rate is auto-set by examining the incoming mclk and lrck/fs signals. lrck/fs and sclk operate as inputs in slave mode. it is recommended that the lrck/fs be synchro- nously derived from the master clock, and it must be equal to the desired sampling rate, fs. dif1 dif0 mode 0 0 left justified 01 i2s 1 0 tdm (2 wire) 1 1 tdm (4 wire) 128 64 m0 m1 lrck/ fs single speed quad speed double speed 00 01 10 2 4 1 sclk single speed quad speed double speed 00 01 10 256 pin cmode md iv n/a mclk 1 1.5 2 1 2 1 bit cmode md iv1 md iv0 0/1 0/1 0/1 mclk dividers sample rate dividers
ds624a1 29 cs5368 4.6.9 master and slave clock frequencies tables 4 through 9 show the clock speeds for sample rates of 48 khz, 96 khz and 192 khz. in master mode, the device outputs the frequencies shown. in slave mode, the sclk/lrck ratio can be set ac- cording to design preference. however, device perfo rmance is guaranteed only when using the ratios shown in the tables . table 4. frequencies for 48 khz sample rate using lj/i2s table 5. frequencies for 96 khz sample rate using lj/i2s table 6. frequencies for 192 khz sample rate using lj/i2s table 7. frequencies for 48 khz sample rate using tdm control port mode only lj/i2s master or slave ssm mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.576 18.384 12.288 sclk(mhz) 3.072 3.072 3.072 3.072 3.072 mclk/lrck ratio 1024 768 512 384 256 sclk/lrck ratio 64 64 64 64 64 lj/i2s master or slave dsm mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk(mhz) 6.144 6.144 6.144 6.144 6.144 mclk/lrck ratio 512 384 256 192 128 sclk/lrck ratio 64 64 64 64 64 lj/i2s master or slave qsm mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24 18.384 12.288 sclk (mhz) 12.288 12.288 12.288 12.288 12.288 mclk/lrck ratio 256 192 128 96 64 sclk/lrck ratio 64 64 64 64 64 tdm master or slave ssm mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 12.288 12.288 12.288 12.288 12.288 mclk/fs ratio 1024 768 512 384 256 sclk/fs ratio 256 256 256 256 256
30 ds624a1 cs5368 table 8. frequencies for 96 khz sample rate using tdm table 9. frequencies for 192 khz sample rate using tdm 4.7 serial audio formats the adc supports i2s, left-justified and tdm digital in terface formats. audio data should be latched by the receiver on the rising edge of sclk within the specified setup and hold times. figure 12. lj format figure 13. i2s format figure 14. tdm format tdm master or slave dsm mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 24.576 24.576 24.576 24.576 24.576 mclk/fs ratio 512 384 256 192 128 sclk/fs ratio 256 256 256 256 256 tdm master or slave qsm mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 49.152 49.152 49.152 49.152 49.152 mclk/fs ratio 256 192 128 96 64 sclk/fs ratio 256 256 256 256 256 odd channels 1,3, ... even channels 2,4, ... lrck receiver latches data on rising edges of sclk msb ... lsb msb msb ... lsb sdout sclk odd channels 1,3, ... even channels 2,4, ... lrck receiver latches data on rising edges of sclk sdout sclk msb ... lsb msb ... lsb msb channel 6 sclk lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb tdm out channel 1 channel 4 channel 2 channel 5 channel 3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks channel 8 lsb msb lsb msb channel 7 32 clks 32 clks fs 256 sclks msb bit or word wide lsb
ds624a1 31 cs5368 4.7.1 lj and i 2 s format the left-justified and i 2 s formats are both two-channel protocols. during one lrck period, two channels of data are transmitted, odd channels first, th en even. the msb is always clocked out first. in slave mode, if more than 32 sclks per channel ar e received from a master controller, the cs5368 will fill the longer frame with trailing zeroes. if fewer than 24 sclks per ch annel are received from a master, the cs5368 will truncate the serial data output to the number of sclks received. 4.7.2 tdm format in tdm mode, all eight channels of audio data are se rially clocked out during a single frame sync (fs) cycle. the rising edge of fs sign ifies the start of a new tdm frame cycl e. each channel slot occupies 32 sclks, with the data left justified and with msb first. tdm output data should both be latched on the rising edge of sclk within the specified setup and hold times. to achieve maximum noise performance, sdout2/tdm should be loaded in the same manner as sdout1/tdm. for the same reason, it is also recommended that the serial clock be synchronously de- rived from the master clock and be equal to 256xfs. 4.8 overflow detection 4.8.1 stand-alone mode the cs5368 includes overflow detection on all input channels. in stand-alone mode, this information is presented as open drain, active low on the ovfl pin. the pin will go to a logica l low as soon as an over- range condition in any channel is detected. th e data will remain low, then timeout as specified in "over- flow timeout" on page 19 . after the timeout, the ovfl pin will return to a logical high if there has not been any other overrange c ondition detect ed. note that an over range condition on any channel will restart the timeout period. 4.8.2 control-port mode in control-port mode, the overflow status register interacts with the overflow mask register to provide interrupt capability for each individual channel. see page 36 for details on these two registers. 4.9 control port operation the control port is used to read and write the internal device registers. it supports two industry standard formats, i2c and spi. the part is in i2c format by default. spi mode is selected if there is ever a high-to-low transition on the ad0/cs pin after the rst pin has been brought high. 4.9.1 spi mode in spi mode, cs is the cs5368 chip select signal; cclk is th e control port bit clock (input into the cs5368 from a controller); cdin is the input data line from a controller; cdout is the output data line to a con- troller. data is clock ed in on the rising edge of cclk and is supplied on the falling edge of cclk. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 1001111. the eighth bit is a read/write indicator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map) , which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the regist er designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? re- sistor, if desired.
32 ds624a1 cs5368 there is a map auto-increm ent capability, which is enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or writes. if incr is set to a 1, the map will auto increment after each byte is read or written, allowing block reads or writes of successive registers. to read a register, the map has to be set to the co rrect address by executing a partial write cycle that finishes (cs high) immediately after the map byte. the map auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map au to increment bit is set to 1, the dat a for successive registers will appear consecutively . figure 15. spi format 4.9.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocke d into and out of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least significant bits of the chip address and should be connected through a resistor to vlc or dgnd as desired. the state of the pins is latched when the cs5368 is being released from rst . a start condition is defined as a falling transition of sda while scl is high. a stop condition is a rising transition of sda while scl is high. all other transition s of sda occur while scl is low. the first byte sent to the cs5368 after a start condition cons ists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper five bits of the 7-bit addr ess field are fixed at 10011. to communicate with a cs5368 , the chip address field, which is the first byte sent to the cs5368, should match 10011 and be followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address po inter (map) which selects the register to be read or written. if the operation is a read, the contents of the register po inted to by the map will be output. setting the auto increment bit in map allows successive reads or writes of co nsecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs5368 after each input byte is read and is input to the cs5368 from the mi crocontroller after each transmitted byte. since the read operation cannot set the map, an abor ted write operation is used as a preamble. the write operation is aborted after the acknowledge for the m ap byte by sending a stop condition. the following pseudocode illustrates an ab orted write operation follo wed by a read operation. send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance
ds624a1 33 cs5368 send stop condition, aborting write. send start condition. send 10011xx1 (chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. figure 16. i 2 c write format figure 17. i 2 c read format 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop
ds624a1 35 cs5368 5. register map in control port mode, the bits in these registers are used to control all of the progr ammable features of the adc. 5.1 register quick reference 5.2 00h (revi) chip id c ode & revision register default: see description the chip id code & revision register is used to store the id and revision of the chip. bits[7:4] contain the chip id, where the cs5368 is represented with a value of 0x8. bits[3:0] contain the revision of the chip, where revision a is represented as 0x0, revision b is represented as 0x1, etc. 5.3 01h (gctl) global mode control register default: 0x00 the global mode control register is used to c ontrol the master/slave speed modes, the serial audio data format and the master clock dividers for all channels. it also contains a control port enable bit. bit[7] cp-en manages the control port mode. until this bit is asserted, all pins behave as if in stand-alone mode. when this bit is asserted, a ll pins used in stand-alone mode are ignored, and the corresponding register values become functional. adr name76543210 00 revi chip-id[3:0] revision[3:0] 01 gctl cp-en clkmode mdiv[1:0] dif[1:0] mode[1:0] 02 ovfl ovfl8 ovfl7 ovfl6 ovfl5 ovfl4 ovfl3 ovfl2 ovfl1 03 ovfm ovfm8 ovfm7 ovfm6 ovfm5 ovfm4 ovfm3 ovfm2 ovfm1 04 hpf hpf8 hpf7 hpf6 hpf5 hpf4 hpf3 hpf2 hpf1 05 reserved -------- 06 pdne not used pdn-bg pdn-osc pdn87 pdn65 pdn43 pdn21 07 reserved -------- 08 mute mute8 mute7 mute6 mute5 mute4 mute3 mute2 mute1 09 reserved -------- 0a sden not used sden4 sden3 sden2 sden1 r/w76543210 r chip-id[3:0] revision[3:0] r/w76543210 r/w cp-en clkmode mdiv[1:0] dif[1:0] mode[1:0]
36 ds624a1 cs5368 bit[6] clkmode setting this bit puts the part in 384x mode (divides xti by 1.5), and clearing the bit invokes 256x mode (divide xti by 1.0 - pass through). bits[5:4] mdiv[1:0] each bit selects an xti divider. when either bit is low, an xti divide by 1 function is selected. when either bit is high, an xti divide by 2 function is selected. with both bits high, xti is divided by 4. the table below shows the composite xti division using both clkmode and mdiv[1:0]. bits[3:2] dif[1:0] determine which data format the serial audio interface is using to clock out da- ta. dif[1:0] 0x00 left justified format 0x01 i2s format 0x02 tdm format 0x03 tdm format bits[1:0] mode[1:0] this bit field determines the device sample rate range and whether it is op- erating as an audio clocking master or slave. mode[1:0] 0x00 single-speed mode master 0x01 double-speed mode master 0x02 quad-speed mode master 0x03 slave mode all speeds 5.4 02h (ovfl ) overflow status register default: 0xff, no over flows have occurred. note: this register interacts with register 03h, the overflow mask register. the overflow status register is used to indicate an individual overflow in a channel. if an overflow condition on any channel is detected, the corresponding bit in this register is asserted (low) in ad- dition to the open drain active low ovfl pin going low. each overflow status bit is sticky and is cleared only when read, providing full interrupt capability. clkmode,mdiv[1],md iv[0] description 000 divide-by-1 100 divide-by-1.5 001 or 010 divide-by-2 101 or 110 divide-by-3 011 divide-by-4 111 unused r/w76543210 rovfl8 ovfl7 ovfl6 ovfl5 ovfl4 ovfl3 ovfl2 ovfl1
ds624a1 37 cs5368 5.5 03h (ovfm) over flow mask register default: 0xff, all over flow interrupts enabled. the overflow mask register is used to allow or prevent individual channel overflow events from creating activity on the ovfl pin. when a particular bit is set low in the mask register, the corresponding overflow bit in the overflow status r egister is prevented from causing any activity on the ovfl pin. 5.6 04h (hpf ) high-pass filter register default: 0x00, all high-pass filters enabled. the high-pass filter register is used to enable or disable a high-pass filter that exists for each channel. these filters are used to perform dc offset calibration, a procedure that is detailed in ?dc offset control? on page 26 . 5.7 05h reserved 5.8 06h (pdn) power down register default: 0x00 - everything powered up the power down register is used as needed to reduce the chip?s power consumption. bit[7] reserved bit[6] reserved bit[5] pdn-bg when set, this bit powers-down the bandgap reference. bit[4] pdn-osc controls power to the internal oscillator core. when asserted, the internal oscil- lator core is shut down, and no cloc k is supplied to the chip. if the ch ip is running off an externally supplied clock at the mclk pin, it is also pr evented from clocking the device internally. bit[3:0] pdn when any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs are forced to all zeroes. r/w76543210 r/w ovfm8 ovfm7 ovfm6 ovfm5 ovfm4 ovfm3 ovfm2 ovfm1 r/w76543210 r/w hpf8 hpf7 hpf6 hpf5 hpf4 hpf3 hpf2 hpf1 r/w76543210 reserved-------- r/w76543210 r/w reserved pdn-bg pdn-osc pdn87 pdn65 pdn43 pdn21
38 ds624a1 cs5368 5.9 07h reserved 5.10 08h (mute) mute control register default: 0x00, no channels are muted. the mute control register is used to mute or un-mute the serial audio data output of individual channels. when a bit is set, that channel?s serial da ta is muted by forcing the output to all zeroes. 5.11 09h reserved 5.12 0ah (sden ) sdout enable control register default: 0x00, all sdout pins enabled. the sdout enable control register is used to tri-state the serial audio data output pins. each bit, when set, tri-states the associated sdout pin. r/w76543210 reserved-------- r/w76543210 r/w mute8 mute7 mute6 mute5 mute4 mute3 mute2 mute1 r/w76543210 reserved-------- r/w76543210 r/w unused sden4 sden3 sden2 sden1
ds624a1 39 cs5368 appendix a digital filter plots figure 18. ssm passband figure 19. dsm passband figure 20. qsm passband 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 frequency (normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 frequency (normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 frequency (normalized to fs) amplitude (db)
40 ds624a1 cs5368 figure 21. ssm stopband figure 22. dsm stopband figure 23. qsm stopband 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (normalized to fs) amplitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (normalized to fs) amplitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (normalized to fs) amplitude (db)
ds624a1 41 cs5368 figure 24. ssm -1 db cutoff figure 25. dsm -1 db cutoff figure 26. qsm -1 db cutoff 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?2 ?1.8 ?1.6 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 frequency (normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?2 ?1.8 ?1.6 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 frequency (normalized to fs) amplitude (db) 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0. 4 ?2 ?1.8 ?1.6 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 frequency (normalized to fs) amplitude (db)
ds624a1 43 cs5368 appendix b parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ra tio measurement over the specified ba ndwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the meas urement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17- 199, and the electronic industries association of ja- pan, eiaj cp-307. expressed in decibels. the dynamic ra nge is specified with and without an a-weighting filter. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion component s. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. sp ecified using an a-weighting filter. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between one channel and all remaining channels, measured for each channel at the con- verter's output with no signal to the input under test a nd a full-scale signal applied to all other channels. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv. intrachannel phase deviation the deviation from linear phase within a given channel. interchannel phase deviation the difference in phase response between channels. .
ds624a1 45 cs5368 appendix c package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds624a1 47 cs5368 table 10. revision history revision date changes a1 july 2005 initial release contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/ important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (?critical applications?). cirr us products are not designed, au thorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer?s ri sk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchan tability and fitness for par ticular purpose, with rega rd to any cirrus product that is used in such a manner. if the customer or customer?s cu stomer uses or permits the use of cirrus products in critical applications, customer agrees, by such u se, to fully indemnify cirrus, its officers , directors, employees, distributors and other agents from any and all liability, including attorneys? fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

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